This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-253888, filed Aug. 24, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, particularly, to the high speed operation of a DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
Various efforts have been made to data in an attempt to develop semiconductor memory devices such as DRAM having a high degree of integration and capable of achieving a high speed operation. On the other hand, the operation margin tends to be lowered because of the lowered power supply voltage caused by the progress of the fine process technology and because of the achievement of the high speed operation. The main reason for the difficulty is that it is difficult to lower the threshold voltage of the transistor in accordance with the lowered power supply voltage. Particularly, under an environment of a low power supply voltage, the operation margin of a circuit in which the wiring of a large capacitance is charged in a short time, e.g., a bit line sense circuit, tends to be lowered.
In order to overcome the problem, a bit line potential overdrive circuit for overdriving the potential of the bit line in charging the bit line has been used. FIGS. 1A and 1B collectively show the construction of the conventional bit line potential overdrive circuit.
FIG. 1A shows the circuit construction of a DRAM, particularly, the memory region relating to the bit line potential overdrive circuit. The memory region of the DRAM shown in FIG. 1A comprises a memory cell array 10 formed by arranging memory cells in the form of a matrix, a row decoder 11, a sense amplifier 12 arranged for column of the memory cell array, a bit line 5 and a complementary bit line 6.
FIG. 1B shows in a magnified fashion the circuit construction of the region denoted by an arrow in FIG. 1A. To be more specific, FIG. 1B shows the typical circuit construction of each of a memory cell, a word line connected to the memory cell, a pair of bit lines, a sense amplifier for driving the bit lines, and an equalize circuit for equalizing the pair of bit lines.
The circuit shown in FIG. 1B comprises an equalize circuit formed of N-channel transistors Q11, Q12, Q13, a sense amplifier formed of P-channel transistors Q1n, Q3n and N-channel transistors Q2n, Q4n (n being a natural number), N-channel transistors Qs1, Qs2, a cell capacitor Cc, and a memory cell formed of a single cell transistor Qc.
Reference numerals 3 and 4 represent an NCS node and a PCS node, respectively. The voltage on the side of the P-channel transistor and the voltage on the side of the N-channel transistor each serving to activate the sense amplifier are applied to the NCS node 3 and the PCN node 4, respectively. Reference numerals 5 and 6 represent a bit line BL and a complementary bit line /BL, respectively. Reference numeral 7 represents a signal line ISO for coupling the sense amplifier and the memory cell. Further, reference numeral 8 represents a word line WL. Incidentally, EQL represents an equalize signal line. If EQL is set at a high level, the potentials of the bit line BL and the complementary bit line /BL are set at VBLEQ, which is half the bit line final potential VBLH.
The conventional bit line potential overdrive circuit, which is directly relevant to the present invention, will now be described with reference to FIG. 2.
The bit line potential overdrive circuit shown in FIG. 2 comprises 0-th to n-th sense amplifiers formed between the PCS node 3 and the NCS node 4, 0-th to n-th bit line pairs driven by these sense amplifiers, a P-channel transistor Q5 serving to impart a bit line overdrive potential VINT to the PCS node upon receipt of a control signal /PSE1, a P-channel transistor Q6 serving to impart a bit line final potential VBLH to the PCS node upon receipt of a control signal /PSET2, and an N-channel transistor Q7 making the NCS node to the ground potential Vss upon receipt of a control signal NSET.
The operation of the conventional bit line potential overdrive circuit will now be described with reference to FIG. 2 with attentions paid to the n-th sense amplifier and the bit line pair. The circuit construction of the n-th sense amplifier consisting of n-th P-channel transistors Q1n, Q3n and n-th N-channel transistors Q2n, Q4n is equal to that shown in FIG. 1B.
AS shown in FIG. 2, in the n-th sense amplifier, the P-channel transistor Q1n and the N-channel transistor Q2n form a first complementary inverter, and the P-channel transistor Q3n and the N-channel transistor Q4n form a second complementary inverter.
The output of the first complementary inverter is connected to the input of the second complementary inverter via the complementary bit line /BL, and the output of the second complementary inverter is fed back to the first complementary inverter via the bit line BL so as to form a sense amplifier consisting of a complementary flip-flop.
The charge stored in the cell capacitor Cc having a miniature capacitance is amplified in the sense amplifier via the cell transistor Qc and the bit line of large wiring capacitance. Also, the stored memory data amplified by the sense amplifier is then restored in the cell capacitor Cc.
In order to rapidly amplify the charge stored in the cell capacitor Cc having a miniature capacitance via a large bit line capacitance, it is effective to add a bit line potential overdrive circuit serving to supply the charge required for changing the bit line in a short time to the sense amplifier.
The operation of the bit line potential overdrive circuit shown in FIG. 2 will now be described more in detail with reference to FIG. 3 showing the timing wave form diagram.
As described previously, power supplies of two systems supplying the bit line overdrive potential VINT and the bit line final potential VBLH (VBLH less than VINT) are prepared for the PCS node of the conventional bit line potential overdrive circuit, and the bit line charging time is shortened by connecting the bit line to the power supply of the overdrive potential VINT higher than the final potential VBLH in the initial stage of the bit line charging.
FIG. 3 exemplifies the operation timing wave form of the bit line overdrive circuit. The operation of the conventional bit line overdrive circuit will now be described with reference to FIG. 3, where (1), (2) and (3) show respective time regions.
(1) Since each of /PSET1 and /PSET2 has a high level (hereinafter referred to as xe2x80x9cHxe2x80x9d), both Q5 and Q6 are in the off-state, NSET has a low level (hereinafter referred to as xe2x80x9cLxe2x80x9d), and Q7 is in the off-state, the sense amplifier is under a stand-by (inactive) state and the potential of each of PCS and NCS is set at VBLH/2. Also, since the word line WLn is xe2x80x9cLxe2x80x9d and Qc is in the off-state, the cell capacitor Cc is separated from the bit line BLn.
(2) Since the states that /PSET1 is xe2x80x9cHxe2x80x9d, /PSET2 is xe2x80x9cHxe2x80x9d, and that NSET is xe2x80x9cLxe2x80x9d are left unchanged, the stand-by state of the sense amplifier is maintained. The word line WLn is set at xe2x80x9cHxe2x80x9d and the charge of the cell capacitor Cc is read on the bit line BLn.
(3) If NSET is set at xe2x80x9cHxe2x80x9d with each of /PSET1 and /PSET2 maintained at xe2x80x9cHxe2x80x9d, the transistor Q7 is turned on so as to activate the N-channel side of the sense amplifier and lower the potential of the complementary bit line /BLn to Vss. Then, if the transistor Q5 is turned on with /SET1 set at xe2x80x9cLxe2x80x9d, the bit line BLn is connected to the power supply of the overdrive potential VINT so as to activate the P-channel side of the sense amplifier. It follows that the potential of the bit line BLn is rapidly elevated. If /PSET1 is brought back to xe2x80x9cHxe2x80x9d so as to turn off the transistor Q5 and, at the same time, /PSET2 is set at xe2x80x9cLxe2x80x9d so as to turn off the transistor Q6 before the potential of the bit line BLn reaches the final potential VBVLH, the power supply connected to the bit line BLn is switched to the power supply for imparting the final potential VBLH of the bit line from VINT.
If the potential of the bit line BLn is overdriven to a potential close to the final potential VBLH until the power supply switching time, it suffices to slightly charge the bit line BLn after the switching to the power supply of the final potential VBLH. It follows that it is possible to ensure a sufficient operation margin in the high speed operation of the DRAM.
As described above, the voltage Vds between the source and the drain of the P-channel transistor included in the sense amplifier can be increased by connecting the power supply of the overdrive potential VINT to the PCS node, making it possible to charge at a high speed the bit line BLn in the initial sensing operations.
However, the conventional bit line potential overdrive circuit gives rise to a problem. Specifically, the conventional bit line potential overdrive circuit requires power supplies of two systems including the power supply for imparting a bit line overdrive potential to each sense amplifier region and the power supply for imparting the bit line final potential and large size transistors of two systems for controlling the connection and the switching of these power supplies. As a result, the wiring area is increased so as to increase the chip size of the DRAM.
What should also be noted is that, in order to prevent the overcharging of the bit line, in which the potential of the bit line BLn becomes higher than the final potential VBLH, it is necessary to switch the path of the power supply before the overdriven bit line potential reaches the final potential VBLH, giving rise to the problem that the power supply noise is increased.
As described above, the conventional bit line potential overdrive circuit requires the power supplies of two systems for each sense amplifier, giving rise to the problem that the chip size of the DRAM is increased. Also, it is necessary to switch the power supplies of the two systems in the vicinity of the final potential of the bit line, giving rise to the problem that the power supply noise is increased.
The semiconductor memory device according to one embodiment of the present invention is constructed such that a VBLH potential generation circuit for generating a bit line final potential VBLH is arranged in bit line potential overdrive circuit, and a bit line overdrive potential higher than the bit line final potential VBLH is supplied to a VBLH power supply line through a first switch so as to allow a power supply inherent in the bit line potential overdrive circuit to be substantially of a single system. Also, in the semiconductor memory device of the present invention, the output of the VBLH potential generation circuit and a charge adjusting capacitance are connected to the VBLH power supply line, and the overdrive potential is transmitted to the VBLH power supply line through the first switch. Further, the potential of the VBLH power supply line is transmitted to one activation node of a sense amplifier through a second switch.
Also, the semiconductor memory device according to the embodiment of the present invention is featured mainly in that the first switch is turned on with the second switch turned off so as to separate the sense amplifier from the VBLH power supply line, thereby pre-charging the total capacitance of the VBLH power supply line from the overdrive potential, followed by transmitting the pre-charged potential to the bit line through one activation node of the sense amplifier by switching the first switch to the off-state and the second switch to the on-state, thereby operating the bit line overdrive circuit.
According to a first aspect of the present invention, there is provided a semiconductor memory device equipped with a bit line overdrive circuit, comprising:
a final potential generation circuit for imparting a final potential after the overdrive to a bit line;
a first switch having one terminal set at an overdrive potential of the bit line higher than the final potential and having the other terminal connected to the output of the final potential generating circuit;
a second switch having one terminal connected to the other terminal of the first switch and having the other terminal connected to one activation node of a sense amplifier; and
a charge adjusting capacitance for adjusting the potential of the bit line, one terminal of the charge adjusting capacitance being connected to the connection points between the first and second switches and the other terminal being set at a predetermined voltage.
According to a second aspect of the present invention, there is provided a bit line overdriving method for a semiconductor memory device, comprising:
setting one terminal of a first switch at a bit line overdrive potential higher than a bit line final potential;
connecting the other terminal of the first switch to the output of the bit line final potential generation circuit;
connecting one terminal of a second switch to the other terminal of the first switch;
connecting the other terminal of the second switch to one activation node of a sense amplifier;
connecting one terminal of a charge adjusting capacitance for adjusting the bit line potential to the connecting point between the first and second switches;
setting the other terminal of the charge adjusting capacitance at a predetermined voltage;
charging the total capacitance at the connecting point between the first and second switches including the charge adjusting capacitance and the capacitance of the bit line final potential generation circuit to the overdrive potential with the first switch turned on and the second switch turned off; and
discharging the charge charged in the total capacitance at the connecting point between the first and second switches to the bit line through one activation node of the sense amplifier with the first switch turned off and the second switch turned on.
Further, according to a third aspect of the present invention, there is provided a bit line overdriving method for a semiconductor memory device, comprising:
charging the total capacitance at the connecting point between the first and second switches including the charge adjusting capacitance and the capacitance of the bit line final potential generation circuit with the first switch turned on and the second switch turned off;
supplying a charging current from a power supply of the overdrive potential to the bit line through one activation node of the sense amplifier by switching the second switch to the on-state while maintaining the on-state of the first switch; and
discharging the charge charged in the total capacitance at the connecting point between the first and second switches to the bit line through one activation node of the sense amplifier by switching the first switch to the off-state while maintaining the on-state of the second switch.